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ds07-13706-1e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90550a series mb90552a/553a/t552a/t553a/f553a/p553a n description the mb90550a series is a line of general-purpose, high-performance, 16-bit microcontrollers designed for appli- cations which require high-speed real-time processing, such as industrial machines, oa equipment, and process control systems. while inheriting the at architecture of the f 2 mc*-8 family, the instruction set for the mb90550a series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, the mb90550a has an on-chip 32-bit accumulator which enables processing of long-word data. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? minimum instruction execution time : 62.5 ns (at oscillation of 4 mhz, four times the pll clock) ? maximum memory space 16 mbytes ? instruction set optimized for controller applications supported data types : bit, byte, word, and long word typical addressing mode : 23 types enhanced precision calculation realized by the 32-bit accumulator enhanced signed multiplication/division instruction and reti instruction functions (continued) n packages 100-pin plastic qfp 100-pin plastic lqfp (fpt-100p-m06) (fpt-100p-m05)
mb90550a series 2 (continued) ? instruction set designed for high level language (c) and multi-task operations adoption of system stack pointer symmetrical instruction set and barrel shift instructions ? address match detection function integrated (for two address pointers) ? faster execution speed : 4-byte queue ? powerful interrupt functions (eight priority levels programmable) external interrupt inputs : 8 channels ? data transfer functions (intelligent i/o service) : up to 16 channels dtp request inputs : 8 channels ? embedded rom size (eprom, flash : 128 kbytes) mask rom : 64 kbytes/128 kbytes ? embedded ram size (eprom, flash : 4 kbytes) mask rom : 2 kbytes/4 kbytes ? general-purpose ports :up to 83 channels (input pull-up resistor settable for : 16 channels open drain settable for : 8 channels i/o open drains : 6 channels) ? a/d converter (rc successive approximation type): 8 channels (resolution: 8 or 10 bits selectable; conversion time of 26.3 m s minimum) ? uart : 1 channel ? extended i/o serial interface : 2 channels ?i 2 c interface : 2 channels (two channels, including one switchable between terminal input and output) ? 16-bit reload timer : 2 channels ? 8/16-bit ppg timer : 3 channels (8 bits 2 channels; 16 bits x 1 channel: mode switching function provided) ? 16-bit i/o timer (input capture 4 channels, output compare 4 channels, free run timer 1 channel ? clock monitor function integrated (delivering the oscillation clock divided by 21 to 28) ? timebase timer/watchdog timer : 18 bit ? low power consumption modes (sleep, stop, hardware standby, and cpu intermittent operation modes) ? package : qfp-100, lqfp-100 ?cmos technology
mb90550a series 3 n product lineup (continued) part number item mb90552a mb90553a mb90f553a mb90p553a mb90v550a classification mask rom products flash rom products otp evaluation product mass product rom size 64 kbytes 128 kbytes none ram size 2 kbytes 4 kbytes 6 kbytes cpu functions the number of instructions: 340 instruction bit length: 8 bits, 16 bits instruction length: 1 byte to 7 bytes data bit length: 1 bit, 8 bits, 16 bits minimum execution time: 62.5 ns (at machine clock of 16 mhz) interrupt processing time: 1.5 ms (at machine clock of 16 mhz, minimum value) ports general-purpose i/o ports (cmos output): 53 general-purpose i/o ports (with pull-up resistor): 16 general-purpose i/o ports (n-channel open-drain output): 6 general-purpose i/o ports (n-channel open-drain function selectable): 8 total: 83 uart0 (sci) clock synchronized transmission (62.5 kbps to 2 mbps) clock asynchronized transmission (62500 bps to 9615 bps) transmission can be performed by bi-directional serial transmission or by master/slave connection. 8/10-bit a/d converter resolution: 8/10-bit number of inputs: 8 one-shot conversion mode (converts selected channel only once) scan conversion mode (converts two or more successive channels and can program up to 8 channels.) continuous conversion mode (converts selected channel continuously) stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit ppg timer number of channels: 1 (or 8-bit 2 channels) ppg operation of 8-bit or 16-bit a pulse wave of given intervals and given duty ratios can be output. pulse interval: 62.5 ns to 1 ms (at oscillation of 4 mhz, machine clock of 16 mhz) 16-bit i/o timer 16-bit free run timer number of channel: 1 overflow interrupts output com- pare (ocu) number of channels: 4 pin input factor: a match signal of compare register input cap- ture (icu) number of channels: 4 rewriting a register value upon a pin input (rising, falling, or both edges)
mb90550a series 4 (continued) *:varies with conditions such as the operating frequency. (see section n electrical characteristics) assurance for the mb90v550a is given only for operation with a tool at a power voltage of 4.5 v to 5.5 v, an operating temperature of 0 to +25 c, and an operating frequency of 1 mhz to 16 mhz. n package and corresponding products : available : not available note:for more information about each package, see section n package dimensions n differences among products memory size in evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. the following items must be taken into consideration. ? the mb90v550a does not have an internal rom, however, operations equivalent to chips with an internal rom can be evaluated by using a dedicated development tool, enabling selection of rom size by settings of the development tool. ? in the mb90v550, images from ff4000 h to ffffff h are mapped to bank 00, and fe0000 h to ff3fff h to mapped to bank fe and ff only. (this setting can be changed by configuring the deveolpment tool.) ? in the mb90f553a/553a/552a, images from ff4000 h to ffffff h are mapped to bank 00, and ff0000 h to ff3fff h to bank ff only. part number item mb90552a mb90553a mb90f553a mb90p553a mb90v550a dtp/external interrupt cir- cuit number of inputs: 8 started by a rising edge, a falling edge, an h level input, or an l level input. external interrupt circuit or extended intelligent i/o service (ei 2 os) can be used. extended i/o serial interface clock synchronized transmission (3125 bps to 1 mbps) lsb first/msb first i 2 c interface serial i/o port for supporting inter ic bus timebase timer 18-bit counter interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 mhz) watchdog timer reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 mhz, minimum value) process cmos power supply voltage for op- eration* 4.5 v to 5.5 v package mb90552a mb90553a mb90f553a mb90p553a fpt-100p-m05 fpt-100p-m06
mb90550a series 5 n pin assignment ? fpt-100p-m06 (top view) (fpt-100p-m06) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p20/a16 p21/a17 p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd v ss p32/wrl p33/wrh p34/hrq p35/hak p36/rdy p37/clk p40/sck p41/sot p42/sin p43/sck1 p44/sot1 v cc p45/sin1 p46/adtg p47/sck0 c p50/sda0/sot0 p51/scl0/sin0 p52/sda1 pa4/ckot pa2 rst pa1/out3 pa0/out2 p97/ppg5 p96/ppg4 p95/ppg3 p94/ppg2 p93/ppg1 p92/ppg0 p91/out1 p92/out0 p87/in3 p86/in2 p85/in1 p84/in0 p83/tot1 p82/tot0 p81/tin1 p80/tin0 p77/irq7 p76/irq6 p75/irq5 p74/irq4 p73/irq3 p72/irq2 hst md2 pa3 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss p53/scl1 p54/sda2 p55/scl2 p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p70/irq0 p71/irq1 md0 md1 av cc avrh avrl av ss
mb90550a series 6 ? fpt-100p-m05 (top view) (fpt-100p-m05) p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd v ss p32/wrl p34/hrq p33/wrh p35/hak p36/rdy p37/clk p40/sck p41/sot p42/sin p43/sck1 p44/sot1 v cc p45/sin1 p46/adtg p47/sck0 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst pa1/out3 pa0/out2 p97/ppg5 p96/ppg4 p95/ppg3 p94/ppg2 p93/ppg1 p92/ppg0 p91/out1 p90/out0 p87/in3 p86/in2 p85/in1 p84/in0 p83/tot1 p82/tot0 p81/tin1 p80/tin0 p77/irq7 p76/irq6 p75/irq5 p74/irq4 p73/irq3 p72/irq2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p21/a17 p20/a16 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss pa4/ckot pa3 pa2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p50/sda0/sot0 p51/scl0/sin0 p52/sda1 p53/scl1 p54/sda2 p55/scl2 av cc avrh avrl av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p70/irq0 p71/irq1 md0 md1 md2 hst
mb90550a series 7 n pin description (continued) pin no. pin name circuit type function qfp lqfp 82 80 x0 a oscillation pin 83 81 x1 a oscillation pin 77 75 rst b reset input pin 52 50 hst c hardware standby input pin 85 to 92 83 to 90 p00 to p07 d (cmos) general-purpose i/o port. a pull-up resistor can be added (rd07 to rd00 = 1) by using the pull-up resistor setting register (rdr0). d07 to d00 = 1: disabled when the port is set for output. ad00 to ad07 serve as lower data i/o/lower address output (ad00 to ad07) pins in the external bus mode. 93 to 100 91 to 98 p10 to p17 d (cmos) general-purpose i/o port. a pull-up resistor can be added (rd17 to rd10 = 1) by using the pull-up resistor setting register (rdr1). d17 to d10 = 1: disabled when the port is set for output. ad08 to ad15 serve as upper data i/o/middle address output (ad08 to ad15) pins in the 16-bit bus-width, external bus mode. 1 to 8 99,100, 1 to 6 p20 to p27 e (cmos) general-purpose i/o port. this function is enabled either in single-chip mode or with the xternal address output control register set to "port". a16 to a23 external address bus a16 to a23 output pins. this function is enabled in an external-bus enabled mode with the external address output register set to "address". 97 p30 e (cmos) general-purpose i/o port. this function is enabled in single-chip mode. ale address latch enable output pin. this function is enabled in an external-bus enabled mode. 10 8 p31 e (cmos) general-purpose i/o port. this function is enabled in single-chip mode. rd read strobe output pin for the data bus. this function is enabled in an external-bus enabled mode. 12 10 p32 e (cmos) general-purpose i/o port. this function is enabled in single-chip mode. wrl write strobe output pin for the lower eight bits of the data bus. this function is enabled in an external-bus enabled mode. 13 11 p33 e (cmos) general-purpose i/o port. this function is enabled in single-chip mode. wrh write strobe output pin for the upper eight bits of the data bus. this function is enabled in an external-bus enabled mode.
mb90550a series 8 (continued) pin no. pin name circuit type function qfp lqfp 14 12 p34 e (cmos) general-purpose i/o port. this function is enabled in single-chip mode hrq hold request input pin. this function is enabled in an external-bus enabled mode. 15 13 p35 e (cmos) general-purpose i/o port. this function is enabled in single-chip mode. hak hold acknowledge output pin. this function is enabled in an external-bus enabled mode. 16 14 p36 e (cmos) general-purpose i/o port. this function is enabled in single-chip mode. rdy ready signal input pin. this function is enabled in an external-bus enabled mode. 17 15 p37 e (cmos) general-purpose i/o port. this function is enabled in single-chip mode. clk clk output pin. this function is enabled in an external-bus enabled mode. 18 16 p40 f (cmos/h) general-purpose i/o port. serves as an open-drain output port (od40 = 1) depending on the setting of the open-drain control setting register (odr4). (d40 = 0: disabled when the port is set for input.) sck uart serial clock i/o pin. this function is enabled with the uart clock output enabled. 19 17 p41 f (cmos/h) general-purpose i/o port. serves as an open-drain output port (od41 = 1) depending on the setting of the open-drain control setting register (odr4). (d41 = 0: disabled when the port is set for input.) sot uart serial data output pin. this function is enabled with the uart serial data output enabled. 20 18 p42 f (cmos/h) general-purpose i/o port. serves as an open-drain output port (od42 = 1) depending on the setting of the open-drain control setting register (odr4). (d42 = 0: disabled when the port is set for input.) sin uart serial data input pin. since this input is used as required while the uart is operating for input, the output by any other func- tion must be off unless used intentionally. 21 19 p43 f (cmos/h) general-purpose i/o port. serves as an open-drain output port (od43 = 1) depending on the setting of the open-drain control setting register (odr4). (d43 = 0: disabled when the port is set for input.) sck1 extended i/o serial clock i/o pin. this function is enabled with the extended i/o serial clock output enabled.
mb90550a series 9 (continued) pin no. pin name circuit type function qfp lqfp 22 20 p44 f (cmos/h) general-purpose i/o port. serves as an open-drain output port (od44 = 1) depending on the setting of the open-drain control setting register (odr4). (d44 = 0: disabled when the port is set for input.) sot1 extended i/o serial data output pin. this function is enabled with the extended i/o serial data output enabled. 24 22 p45 f (cmos/h) general-purpose i/o port. serves as an open-drain output port (od45 = 1) depending on the setting of the open-drain control setting register (odr4). (d45 = 0: disabled when the port is set for input.) sin1 extended i/o serial data input pin. since this input is used as required while the extended i/o serial interface is operating for input, the output by any other function must be off unless used intentionally. 25 23 p46 f (cmos/h) general-purpose i/o port. serves as an open-drain output port (od46 = 1) depending on the setting of the open-drain control setting register (odr4). (d46 = 0: disabled when the port is set for input.) adtg a/d converter external trigger input pin. since this input is used as required while the a/d converter is op- erating for input, the output by any other function must be off un- less used intentionally. 26 24 p47 f (cmos/h) general-purpose i/o port. serves as an open-drain output port (od47 = 1) depending on the setting of the open-drain control setting register (odr4). d47 = 0: disabled when the port is set for input. sck0 extended i/o serial clock i/o pin. this function is enabled with the extended i/o serial clock output enabled. 27 25 c capacitance pin for regulating the power supply. connect an external ceramic capacitor of about 0.1 m f. 28 26 p50 g (nchod/h) n-channel open-drain i/o port. sda0 i 2 c interface data i/o pin. this function is enabled with the i 2 c interface enabled for operation. while the i 2 c interface is operating, place the port output in the hi-z state (pdr = 1). sot0 extended i/o serial data output pin. this function is enabled with the extended i/o serial data output enabled.
mb90550a series 10 (continued) pin no. pin name circuit type function qfp lqfp 29 27 p51 g (nchod/h) n-channel open-drain i/o port. scl0 i 2 c interface clock i/o pin. this function is enabled with the i 2 c interface enabled for operation. while the i 2 c interface is operating, place the port output in the hi-z state (pdr = 1). sin0 extended i/o serial data input pin. since this input is used as required while the extended i/o serial interface is operating for input, the output by any other function must be off unless used intentionally. 30,32 28,30 p52,p54 g (nchod/h) n-channel open-drain i/o port. sda1,sda2 i 2 c interface data i/o pins. this function is enabled with the i 2 c interface enabled for operation. while the i 2 c interface is operating, place the port output in the hi-z state (pdr = 1). 31,33 29,31 p53,p55 g (nchod/h) n-channel open-drain i/o port. scl1,scl2 i 2 c interface clock i/o pins. this function is enabled with the i 2 c interface enabled for operation. while the i 2 c interface is operating, place the port output in the hi-z state (pdr = 1). 38 to 41, 43 to 46 36 to 39, 41 to 44 p60 to p67 h (cmos/h) general-purpose i/o port. an0 to an7 a/d converter analog input pin. this function is enabled with the analog input enabled. 47,48, 53 to 58 45,46, 51 to 56 p70 to p77 i (cmos/h) general-purpose i/o port. irq0 to irq7 external interrupt request input pins. since this input is used as required while external interrupts remain enabled, the output by any other function must be off unless used intentionally. 59,60 57,58 p80,p81 j (cmos/h) general-purpose i/o port. tin0,tin1 reload timer event input pins. since this input is used as required while the reload timer is operating for input, the output by any other function must be off unless used intentionally. 61,62 59,60 p82,p83 j (cmos/h) general-purpose i/o port. tot0,tot1 reload timer output pins. 63 to 66 61 to 64 p84 to p87 j (cmos/h) general-purpose i/o port. in0 to in3 input capture trigger input pin. since this input is used as required while the input capture unit is operating for input, the output by any other function must be off unless used intentionally. 67,68 65,66 p90,p91 j (cmos/h) general-purpose i/o port. out0,out1 output compare event output pins.
mb90550a series 11 (continued) pin no. pin name circuit type function qfp lqfp 69 to 74 67 to 72 p92 to p97 j (cmos/h) general-purpose i/o port. ppg0 to ppg5 ppg output pins. this function is enabled with the ppg output enabled. 75,76 73,74 pa0,pa1 j (cmos/h) general-purpose i/o port. out2,out3 output compare event output pins. 78,79 76,77 pa2,pa3 j (cmos/h) general-purpose i/o port. 80 78 pa4 j (cmos/h) general-purpose i/o port. ckot serves as the ckot output while the ckot is operating. 34 32 av cc ? a/d converter power-supply pin. 35 33 avrh ? this is a general purpose i/o port. 36 34 avrl ? a/d converter external reference voltage source pin. 37 35 av ss ? a/d converter power-supply pin. 49 to 50 47 to 48 md0,md1 c operation mode setting input pins. connect these pins directly to vcc or vss. 51 49 md2 k operation mode setting input pin. connect this pin directly to vcc or vss. (mb90552a/553a/ v550a) c operation mode setting input pin. connect this pin directly to vcc or vss. (mb90p553a/f553a) 23,84 21,82 v cc ? power (5 v) input pin. 11,42, 81 9,40, 79 v ss ? power (0 v) input pin.
mb90550a series 12 n i/o circuit type (continued) type circuit remarks a ? 3 mhz to 32 mhz ? oscillator recovery resistor approx. 1m w b ? cmos level hysteresis input ? pull-up resistor provided resistor : about 50 k w c ? cmos level hysteresis input d ? cmos level output ? cmos level input ? standby control provided ? input pull-up resistor control provided resistor: about 50 k w x1 x0 hard,soft standby control clock input hard,soft standby control digital input digital output digital output pull-up resistor control
mb90550a series 13 (continued) type circuit remarks e ? cmos level output ? cmos level input ? standby control provided f ? cmos level output ? cmos level hysteresis input ? open-drain control provided g ? n-channel open-drain output ? cmos level hysteresis input ? standby control provided note: unlike normal cmos i/o pins, this pin is not provided with any p-channel transistor. therefore the pin does not allow a current to flow to the vcc side even when applied with a voltage from an external device with the ics power supply left off. h ? cmos level output ? cmos level hysteresis input ? standby control provided ? analog input hard,soft standby control digital output digital output digital input hard,soft standby control digital input digital input open- drain control signal hard,soft standby control digital output digital input hard,soft standby control a/d disable digital output digital output analog input digital input
mb90550a series 14 (continued) type circuit remarks i ? cmos level output ? cmos level hysteresis input ? standby control provided j ? cmos level output ? cmos level hysteresis input ? standby control provided k ? cmos level hysteresis input ? pull-up resistor provided resistor : about 50k w hard standby control digital output digital output digital input hard,soft standby control digital output digital output digital input
mb90550a series 15 n handling devices 1. preventing latchup cmos ics may cause latchup in the following situations: ? when a voltage higher than vcc or lower than vss is applied to input or output pins. ? when a voltage exceeding the rating is applied between vcc and vss. ? when avcc power is supplied prior to the vcc voltage. if latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. use meticulous care not to let it occur. for the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage. 2. connection of unused pins leaving unused pins open may result in abnormal operations. clamp the pin level by connecting it to a pull-up or a pull-down 1k w or more resistor. 3. notes on using external clock in using the external clock, drive x0 pin only and leave x1 pin unconnected. 4. power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. however, connect the pins external power and ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 m f between v cc and v ss pin near the device. ? using external clock mb90550a series x0 x1 open v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss ? using power supply pins mb90550a series
mb90550a series 16 5. crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with an grand area for stabilizing the operation. 6. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply, d/a converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an7) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage not exceed avrh or av cc (turning on/off the analog and digital power supplies simultaneously is acceptable). 7. connection of unused pins of a/d converter connect unused pin of a/d converter to av cc = v cc , av ss = avrh = avrl = v ss . 8. n.c. pin the n.c. (internally connected) pin must be opened for use. 9. notes on energization to prevent the internal regulator circuit rom malfunctioning,set the voltage rise time during energization at 50 or more m s. 10. initialization in the device, there are internal registers which is initialized only by a power-on reset. to initialize these registers turning on the power again. 11. return from standby state if the power-supply voltage goes below the standby ram holding voltage in the standby state, the device may fail to return from the standby state. in this case, reset the device via the external reset pin to return to the normal state. 12. precautions for use of div a, ri, and divw a, ri instructions the signed multiplication-division instructions div a, ri, and divw a, rwi should be used when the corre- sponding bank registers (dtb, adb, usb, ssb) are set to value 00h. if the corresponding bank registers (dtb, adb, usb, ssb) are set to a value other than 00h, then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register.
mb90550a series 17 n block diagram x0, x1 rst hst 4 p00 to p07/ ad00 to ad07 p10 to p17/ ad08 to ad15 p20 to p27/ a16 to a23 p30/ale p31/rd p32/wrl p33/wrh p34/hrq p35/hak p36/rdy p37/clk ckot/pa4 pa2, a3 out2, out3/ pa0, a1 ppg5/p97 ppg4/p96 ppg3/p95 ppg2/p94 ppg1/p93 ppg0/p92 out0, out1/ p90, p91 in0 to in3/ p84 to p87 tot0, tot1/ p82, p83 tin0, tin1/ p80, p81 irq0 to irq7/ p70 to p77 an0 to an7/ p60 to p67 av cc avrh, avrl av ss p40/sck p41/sot p42/sin p43/sck1 p44/sot1 p45/sin1 p46/adtg p47/sck0 p50/sda0/sot0 p51/scl0/sin0 p52/sda1 p53/scl1 p54/sda2 p55/scl2 rom ram uart f f m c 16 l x b u s clock control circuit* port 0 port 1 port 2 port 3 port 4 communication prescaler extended i/o serial interface 1 extended i/o serial interface 0 i 2 c interface 0 i 2 c interface 1 port 5 cpu core of f 2 mc-16lx family interrupt controller port a clock monitor function port 9 8/16 ppg 3c h i/o timer 16-bit output compare unit x 4 channels 16-bit input capture unit x 4 channels 16-bit free-run timer 16-bit reload timer x 2 channels port 8 port 7 external interrupt a/d converter (8/10 bits) port 6 *: s pecifications of evaluation model (mb90v550a) contains no internal rom. contains 6 kb of internal ram. contains the same internal resources as the other products in the mb90550a series.
mb90550a series 18 note: the clock control circuit contains a watchdog timer, time-base timer, and a low power consumption control circuit. p00 to p07 (8 pins): input pull-up resistor setting register provided p10 to p17 (8 pins): input pull-up resistor setting register provided p40 to p47 (8 pins): open-drain control setting register provided p50 to p55 (6 pins): n-channel open drain ports 0, 1, 2, 3, 4, 6, 7, 8, 9, and a are cmos level input/output ports.
mb90550a series 19 n memory map the rom data of bank ff is reflected in the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit of bank ff and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the rom without stating far. for example, if an attempt has been made to access 00c000 h , the contents of the rom at ffc000 h are accessed actually. since the rom area of the ff bank exceeds 48 kbytes, the whole area cannot be reflected in the image for the 00 bank. the rom data at ff4000 h to ffffff h looks, therefore, as if it were the image for 004000 h to 00ffff h . thus, it is recommended that the rom data table be stored in the area of ff4000 h to ffffff h . ram ram ram : internal access memory : external access memory : inhibited area single chip mode a mirror function is supported internal rom external bus mode a mirror function is supported external rom external bus mode ffffff h ff0000 h 010000 h address#1 address#2 address#3 004000 h 002000 h 000100 h 0000c0 h 0000d0 h rom area rom area rom area (image of bank ff) rom area (image of bank ff) peripheral peripheral peripheral registor registor registor parts no. address#1 address#2 address#3 mb90552a ff0000 h 004000 h 000900 h mb90553a fe0000 h 004000 h 001100 h mb90f553a fe0000 h 004000 h 001100 h mb90p553a fe0000 h 004000 h 001100 h mb90v550a (fe0000 h ) 004000 h 001900 h
mb90550a series 20 n f 2 mc-16lx cpu programming model ? dedicated registers ah al usp ssp ps pc dpr pcb dtb usb ssb adb 8 bit 16 bit 32 bit : accumlator (a) dual 16-bit register used for storing results of calculation etc. the two 16-bit registers can be combined to be used as a 32-bit register. : additional data bank register (adb) the 8-bit register indicating the additional data space. : user stack bank register (usb) the 8-bit register indicating the user stack space. : system stack pointer (ssp) the 16-bit pointer indicating the status of the system stack address. : processor status (ps) the 16-bit register indicating the system status. : program bank register (pcb) the 8-bit register indicating the program space. : data bank register (dtb) the 8-bit register indicating the data space. : program counter (pc) the 16-bit register indicating storing location of the current instruction code. : direct page register (dpr) the 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. : system stack bank register (ssb) the 8-bit register indicating the system stack space. : user stack pointer (usp) the 16-bit pointer indicating a user stack address.
mb90550a series 21 n i/o map (continued) address register name abbreviated register name read/write resource name initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx 05 h port 5 data register pdr5 r/w port 5 _ _ 1 1 1 1 1 1 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx 07 h port 7 data register pdr7 r/w port 7 xxxxxxxx 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx 0a h port a data register pdra r/w port a _ _ _xxxxx 0b h to 0f h (disabled) 10 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 11 h port 1 direction register ddr1 r/w port 1 0 0 0 0 0 0 0 0 12 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 0 0 13 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 14 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 15 h (disabled) 16 h port 6 direction register ddr6 r/w port 6 0 0 0 0 0 0 0 0 17 h port 7 direction register ddr7 r/w port 7 0 0 0 0 0 0 0 0 18 h port 8 direction register ddr8 r/w port 8 0 0 0 0 0 0 0 0 19 h port 9 direction register ddr9 r/w port 9 0 0 0 0 0 0 0 0 1a h port a direction register ddra r/w port a _ _ _ 0 0 0 0 0 1b h port 4 output pin register odr4 r/w port 4 0 0 0 0 0 0 0 0 1c h port 0 resistor setting register rdr0 r/w port 0 0 0 0 0 0 0 0 0 1d h port 1 resistor setting register rdr1 r/w port 1 0 0 0 0 0 0 0 0 1e h (disabled) 1f h analog input enable register ader r/w port 6, a/d converter 1 1 1 1 1 1 1 1 20 h serial mode register smr r/w uart 0 0 0 0 0 0 0 0 21 h serial control register scr r/w 0 0 0 0 0 10 0 22 h serial input data register / serial output data register sidr/sodr r/w xxxxxxxx 23 h serial status register ssr r/w 0 0 0 0 1 _ 0 0
mb90550a series 22 (continued) address register name abbreviated register name read/write resource name initial value 24 h serial mode control status register 0 smcs0 r/w extended i/o serial interface 0 _ _ _ _ 0 0 0 0 25 h serial mode control status register 0 r/w! 0 0 0 0 0 0 1 0 26 h serial data register 0 sdr0 r/w xxxxxxxx 27 h clock frequency-divider control register cdcr r/w communication prescaler 0 _ _ _ 1 1 1 1 28 h serial mode control status register 1 smcs1 r/w extended i / o serial interface 1 _ _ _ _ 0 0 0 0 29 h serial mode control status register 1 r/w! 0 0 0 0 0 0 1 0 2a h serial data register 1 sdr1 r/w xxxxxxxx 2b h (disabled) 2c h i 2 c bus status register 0 ibsr0 r i 2 c interface 0 0 0 0 0 0 0 0 0 2d h i 2 c bus control register 0 ibcr0 r/w 0 0 0 0 0 0 0 0 2e h i 2 c bus clock select register 0 iccr0 r/w _ _ 0xxxxx 2f h i 2 c bus address register 0 iadr0 r/w _ xxxxxxx 30 h i 2 c bus data register 0 idar0 r/w xxxxxxxx 31 h (disabled) 32 h i 2 c bus status register 1 ibsr1 r i 2 c interface 1 0 0 0 0 0 0 0 0 33 h i 2 c bus control register 1 ibcr1 r/w 0 0 0 0 0 0 0 0 34 h i 2 c bus clock select register 1 iccr1 r/w _ _ 0xxxxx 35 h i 2 c bus address register 1 iadr1 r/w _ xxxxxxx 36 h i 2 c bus data register 1 idar1 r/w xxxxxxxx 37 h i 2 c bus port select register isel r/w _ _ _ _ _ _ _ 0 38 h interrupt/dtp enable register enir r/w dtp/externalint interrupt 0 0 0 0 0 0 0 0 39 h interrupt/dtp factor register eirr r/w xxxxxxxx 3a h request level setting register elvr r/w 0 0 0 0 0 0 0 0 3b h 0 0 0 0 0 0 0 0 3c h control status register adcs0 r/w a/d convertor 0 0 0 0 0 0 0 0 3d h adcs1 r/w 0 0 0 0 0 0 0 0 3e h data register adcr0 r/w! xxxxxxxx 3f h adcr1 r/w xxxxxxxx
mb90550a series 23 (continued) address register name abbreviated register name read/write resource name initial value 40 h reload register l (ch.0) prll0 r/w 8/16 bit ppg0/1 xxxxxxxx 41 h reload register h (ch.0) prlh0 r/w xxxxxxxx 42 h reload register l (ch.1) prll1 r/w xxxxxxxx 43 h reload register h (ch.1) prlh1 r/w xxxxxxxx 44 h ppg0 operating mode control register ppgc0 r/w 0 _ 0 0 0 _ _ 1 45 h ppg1 operating mode control register ppgc1 r/w 0 _ 0 0 0 0 0 1 46 h ppg0 and 1 output control register ppge1 r/w 0 0 0 0 0 0 0 0 47 h (disabled) 48 h reload register l (ch.2) prll2 r/w 8/16 bit ppg2/3 xxxxxxxx 49 h reload register h (ch.2) prlh2 r/w xxxxxxxx 4a h reload register l (ch.3) prll3 r/w xxxxxxxx 4b h reload register h (ch.3) prlh3 r/w xxxxxxxx 4c h ppg2 operating mode control register ppgc2 r/w 0 _ 0 0 0 _ _ 1 4d h ppg3 operating mode control register ppgc3 r/w 0 _ 0 0 0 0 0 1 4e h ppg2 and 3 output control register ppge2 r/w 0 0 0 0 0 0 0 0 4f h (disabled) 50 h reload register l (ch.4) prll4 r/w 8/16 bit ppg4/5 xxxxxxxx 51 h reload register h (ch.4) prlh4 r/w xxxxxxxx 52 h reload register l (ch.5) prll5 r/w xxxxxxxx 53 h reload register h (ch.5) prlh5 r/w xxxxxxxx 54 h ppg4 operating mode control register ppgc4 r/w 0 _ 0 0 0 _ _ 1 55 h ppg5 operating mode control register ppgc5 r/w 0 _ 0 0 0 0 0 1 56 h ppg4 and 5 output control register ppge3 r/w 0 0 0 0 0 0 0 0 57 h (disabled) 58 h clock output enable register clkr r/w clock monitor function _ _ _ _ 0 0 0 0 59 h (disabled)
mb90550a series 24 (continued) address register name abbreviated register name read/write resource name initial value 5a h control status register 0 tmcsr0 r/w 16 bit reload timer 0 0 0 0 0 0 0 0 0 5b h _ _ _ _ 0 0 0 0 5c h 16 bit timer register 0/ 16 bit reload register 0 tmr0/ tmrlr0 r/w xxxxxxxx 5d h xxxxxxxx 5e h control status register 1 tmcsr1 r/w 16 bit reload timer 1 0 0 0 0 0 0 0 0 5f h _ _ _ _ 0 0 0 0 60 h 16 bit timer register 1/ 16 bit reload register 1 tmr1/ tmrlr1 r/w xxxxxxxx 61 h xxxxxxxx 62 h input capture register, channel-0 lower bits ipcp0 r 16 bit i/o timer input capture (ch.0 to ch.3) xxxxxxxx 63 h input capture register, channel-0 upper bits xxxxxxxx 64 h input capture register, channel-1 lower bits ipcp1 r xxxxxxxx 65 h input capture register, channel-1 upper bits xxxxxxxx 66 h input capture register, channel-2 lower bits ipcp2 r xxxxxxxx 67 h input capture register, channel-2 upper bits xxxxxxxx 68 h input capture register, channel-3 lower bits ipcp3 r xxxxxxxx 69 h input capture register, channel-3 upper bits xxxxxxxx 6a h input capture control status register ics01 r/w 0 0 0 0 0 0 0 0 6b h input capture control status register ics23 r/w 0 0 0 0 0 0 0 0 6c h timer data register, lower bits tcdt r/w 16 bit i/o timer free run timer 0 0 0 0 0 0 0 0 6d h timer data register, upper bits r/w 0 0 0 0 0 0 0 0 6e h timer control status register tccs r/w 0 0 0 0 0 0 0 0 6f h rom mirroring function selection register romm w rom mirroring function _ _ _ _ _ _ _ 1
mb90550a series 25 (continued) address register name abbreviated register name read/write resource name initial value 70 h compare register, channel-0 lower bits occp0 r/w 16 bit i/o timer output compare (ch.0 to ch.3) xxxxxxxx 71 h compare register, channel-0 upper bits xxxxxxxx 72 h compare register, channel-1 lower bits occp1 r/w xxxxxxxx 73 h compare register, channel-1 upper bits xxxxxxxx 74 h compare register, channel-2 lower bits occp2 r/w xxxxxxxx 75 h compare register, channel-2 upper bits xxxxxxxx 76 h compare register, channel-3 lower bits occp3 r/w xxxxxxxx 77 h compare register, channel-3 upper bits xxxxxxxx 78 h compare control status register, channel-0 ocs0 r/w 0 0 0 0 _ _ 0 0 79 h compare control status register, channel-1 ocs1 r/w _ _ _ 0 0 0 0 0 7a h compare control status register, channel-2 ocs2 r/w 0 0 0 0 _ _ 0 0 7b h compare control status register, channel-3 ocs3 r/w _ _ _ 0 0 0 0 0 7c h to 9d h (disabled) 9e h program address detection control register pa c s r r / w address match detection function 0 0 0 0 0 0 0 0 9f h delayed interrupt factor generation/cancellation register dirr r/w delayed interrupt _ _ _ _ _ _ _ 0 a0 h low-power consumption mode control register lpmcr r/w! low power consumption control circuit 0 0 0 1 1 0 0 0 a1 h clock select register ckscr r/w! 1 1 1 1 1 1 0 0 a2 h to a4 h (disabled) a5 h automatic ready function select register arsr w external bus pin control circuit 0 0 1 1 _ _ 0 0 a6 h external address output control register hacr w 0 0 0 0 0 0 0 0 a7 h bus control signal select register ecsr w 0 0 0 0 0 0 0 _
mb90550a series 26 (continued) address register name abbreviated register name read/write resource name initial value a8 h watchdog timer control register wdtc r/w! watchdog timer xxxxx 1 1 1 a9 h timebase timer control register tbtc r/w! timebase timer 1 _ _ 0 0 1 0 0 aa h to ad h (disabled) ae h flash control status register fmcs r/w flash interface circuit 0 0 0 0 0 _ _ 0 af h (disabled) b0 h interrupt control register 00 icr00 r/w! interrupt controller 0 0 0 0 0 1 1 1 b1 h interrupt control register 01 icr01 r/w! 0 0 0 0 0 1 1 1 b2 h interrupt control register 02 icr02 r/w! 0 0 0 0 0 1 1 1 b3 h interrupt control register 03 icr03 r/w! 0 0 0 0 0 1 1 1 b4 h interrupt control register 04 icr04 r/w! 0 0 0 0 0 1 1 1 b5 h interrupt control register 05 icr05 r/w! 0 0 0 0 0 1 1 1 b6 h interrupt control register 06 icr06 r/w! 0 0 0 0 0 1 1 1 b7 h interrupt control register 07 icr07 r/w! 0 0 0 0 0 1 1 1 b8 h interrupt control register 08 icr08 r/w! 0 0 0 0 0 1 1 1 b9 h interrupt control register 09 icr09 r/w! 0 0 0 0 0 1 1 1 ba h interrupt control register 10 icr10 r/w! 0 0 0 0 0 1 1 1 bb h interrupt control register 11 icr11 r/w! 0 0 0 0 0 1 1 1 bc h interrupt control register 12 icr12 r/w! 0 0 0 0 0 1 1 1 bd h interrupt control register 13 icr13 r/w! 0 0 0 0 0 1 1 1 be h interrupt control register 14 icr14 r/w! 0 0 0 0 0 1 1 1 bf h interrupt control register 15 icr15 r/w! 0 0 0 0 0 1 1 1 c0 h to ff h (external area) 100 h to # h (ram area) # h to 1fef h (reserved area)
mb90550a series 27 (continued) ? initial value representations 0: initial value of 0 1: initial value of 1 x: initial value undefined C: initial value undefined (none) ? addresses that follow 00ffh are a reserved area. ? the boundary # h between the ram and reserved areas is different depending on each product. note : for writable bits, the initial value column contains the initial value to which the bit is initialized at a reset. notice that it is not the value read from the bit. the lpmcr, ckscr, and wdtc registers may be initialized or not at a reset, depending on the type of the reset. their initial values in the above list are those to which the registers are initialized, of course. r/w! in the access column indicates that the register contains read-only or write-only bits. if a read-modify-write instruction (such as a bit setting instruction) is used to access a register marked r/ w! r/w*, or w in the access column, the bit focused on by the instruction is set to the desired value but a malfunction occurs if the other bits contains a write-only bit. do not use such instructions to access those registers. address register name abbreviated register name read/write resource name initial value 1ff0 h program address detection register 0 padr0 r/w address match detection function xxxxxxxx 1ff1 h program address detection register 1 r/w xxxxxxxx 1ff2 h program address detection register 2 r/w xxxxxxxx 1ff3 h program address detection register 3 padr1 r/w xxxxxxxx 1ff4 h program address detection register 4 r/w xxxxxxxx 1ff5 h program address detection register 5 r/w xxxxxxxx 1ff6 h to 1fff h (reserved area)
mb90550a series 28 n interrupt factors interrupt vectors, interrupt control registers : the interrupt request flag is cleared by the ei 2 os interrupt clear signal. : the interrupt request flag is not cleared by the ei 2 os interrupt clear signal. : the interrupt request flag is cleared by the ei 2 os interrupt clear signal. the stop request is available. interrupt source ei 2 os support interrupt vectors interrupt control registers number address icr address reset # 08 ffffdc h int9 instruction # 09 ffffd8 h exception # 10 ffffd4 h a/d converter # 11 ffffd0 h icr00 0000b0 h timebase timer # 12 ffffcc h dtp0 (external interrupt 0) # 13 ffffc8 h icr01 0000b1 h dtp4/5 (external interrupt 4/5) # 14 ffffc4 h dtp1 (external interrupt 1) # 15 ffffc0 h icr02 0000b2 h 8/16-bit ppg timer0 counter borrow # 16 ffffbc h dtp2 (external interrupt 2) # 17 ffffb8 h icr03 0000b3 h 8/16-bit ppg timer 1 counter borrow # 18 ffffb4 h dtp3 (external interrupt 3) # 19 ffffb0 h icr04 0000b4 h 8/16-bit ppg timer 2 counter borrow # 20 ffffac h extended i/o serial interface 0 # 21 ffffa8 h icr05 0000b5 h 8/16-bit ppg timer 3 counter borrow # 22 ffffa4 h extended i/o serial interface 1 # 23 ffffa0 h icr06 0000b6 h 16-bit free-run timer (i/o timer) overflow # 24 ffff9c h 16-bit re-load timer 0 # 25 ffff98 h icr07 0000b7 h dtp6/7 (external interrupt 6/7) # 26 ffff94 h 16-bit re-load timer 1 # 27 ffff90 h icr08 0000b8 h 8/16-bit ppg timer 4/5 counter borrow # 28 ffff8c h input capture (ch.0) include (i/o timer) # 29 ffff88 h icr09 0000b9 h input capture (ch.1) include (i/o timer) # 30 ffff84 h input capture (ch.2) include (i/o timer) # 31 ffff80 h icr10 0000ba h input capture (ch.3) include (i/o timer) # 32 ffff7c h output compare (ch.0) match (output timer) #33 ffff78 h icr11 0000bb h output compare (ch.1) match (output timer) # 34 ffff74 h output compare (ch.2) match (output timer) # 35 ffff70 h icr12 0000bc h output compare (ch.3) match (output timer) # 36 ffff6c h uart0 transmission complete # 37 ffff68 h icr13 0000bd h i 2 c interface 0 # 38 ffff64 h uart0 reception complete # 39 ffff60 h icr14 0000be h i 2 c interface 1 # 40 ffff5c h flash memory status # 41 ffff58 h icr15 0000bf h delayed interrupt generation module # 42 ffff54 h
mb90550a series 29 note: on using the ei 2 os function with extended i/o serial interface 2 if a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the ei 2 os interrupt clear signal. when the ei 2 os function is used for one of the two interrupt sources, therefore, the other interrupt function cannot be used. set the interrupt request enable bit for the relevant resource to 0 for software polling processing. interrupt source interrupt no. interrupt control register resource interrupt request extended i/o serial interface 1 # 23 icr06 enabled 16-bit free-run timer (i/o timer) overflow # 24 disabled
mb90550a series 30 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : be careful not to let avcc exceed vcc, for example, when the power supply is turned on. *2 : the maximum output current is a peak value for a corresponding pin. *3 : average output current is an average current value observed for a 100 ms period for a corresponding pin. *4 : total average current is an average current value observed for a 100 ms period for all corresponding pins. *5 : average output current = operating current operating efficiency warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc 3 av cc *1 avrh v ss - 0.3 v ss + 6.0 v av cc 3 avrh 3 avrl avrl v ss - 0.3 v ss + 6.0 v input voltage v i v ss - 0.3 v cc + 0.3 v output voltage v o v ss - 0.3 v cc + 0.3 v l level maximum output current * 2 i ol1 ? 10 ma other than p20 to p27 i ol2 ? 20 ma p20 to p27 l level average output current i olav1 ? 4 ma other than p20 to p27 i olav2 ? 12 ma p20 to p27 l level total maximum output current ? i ol ? 150 ma l level total average output current ? i olav ? 80 ma *5 h level maximum output current i oh * 2 ?- 15 ma h level average output current i ohav * 3 ?- 4ma*5 h level total maximum output current ? i oh ?- 100 ma h level total average output current ? i ohav * 4 ?- 50 ma *5 power consumption p d ? 500 mw operating temperature t a - 40 + 85 c storage temperature t stg - 55 + 150 c
mb90550a series 31 2. recommended operating conditions (v ss = av ss = 0.0 v) *1 : p00 to p07, p10 to p17, p20 to p27, p30 to p37 *2 : x0, hst , rst , p40 to p47, p50 to p55, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 to pa4 *3 : md0, md1, md2 *4 : for connecting smoothing capacitor c s , see the diagram below: *5 : use a ceramic capacitor or a capacitor with equivqlent frequency characteristics. the smoothing capacitor to be connected to the v cc pin must have a capacitance value higher than c s . warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc av cc 4.5 5.5 v normal operation (mb90f553a, mb90p553a, mb90v550a) 3.5 5.5 v normal operation (mb90553a, mb90552a) 3.5 5.5 v retains status at the time of operation stop h level input voltage v ih 0.7v cc v cc + 0.3 v cmos input pin*1 v ihs 0.8v cc v cc + 0.3 v cmos hysteresys input pin*2 v ihm v cc - 0.3 v cc + 0.3 v md pin input*3 l level input voltage v il v ss - 0.3 0.3v cc v cmos input pin*1 v ils v ss - 0.3 0.2v cc v cmos hysteresys input pin*2 v ilm v ss - 0.3 v ss + 0.3 v md pin input*3 smoothing capacitor*4 c s 0.1 1.0 m f*5 operating temperature t a C40 +85 c c c s v ss av ss ? c pin connection circuit
mb90550a series 32 3. dc characteristics (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = C40 c to +85 c) * : the current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. the power supply current is measured with an external clock. parameter symbol pin name condition value unit remarks min. typ. max. open-drain output pin voltage v d p50 to p55 v ss C 0.3 v ss + 6.0 v h level out- put voltage v oh other than p50 to p55 v cc = 4.5v, i oh = - 4.0ma v cc C 0.5 v l level output voltage 1 v ol1 other than p20 to p27 v cc = 4.5v, i ol = 4.0ma 0.4v l level output voltage 2 v ol2 p20 to p27 v cc = 4.5v, i ol = 12.0ma 0.4v input leakage current i il all output pins v cc = 5.5v, v ss < v i < v cc C5 5 m a power supply cur- rent* i cc v cc internal operation at 16 mhz v cc = 5.5 v normal operation 3040ma mb90v550a 80 110 ma mb90p553a 6090ma mb90f553a 3040ma mb90553a 2535ma mb90552a when data writ- ten in flash mode 100 150 ma mb90f553a i ccs internal operation at 16 mhz v cc = 5.5 v in sleep mode 710ma mb90v550a 2530ma mb90p553a 1020ma mb90f553a 710ma mb90553a 710ma mb90552a i cch v cc = 5.5v, t a = + 25 c in stop mode 520 m a mb90v550a 0.110 m a mb90p553a 520 m a mb90f553a 520 m a mb90553a 520 m a mb90552a input capacitance c in other than av cc , av ss , c, v cc and v ss 10pf open-drain output leakage current i leak p50 to p55 0.1 5 m a pull-up resistance r up p00 to p07 and p10 to p17 (in pull-up setting),rst 25 50 100 k w other than mb90v550a 20 40 100 k w mb90v550a
mb90550a series 33 4. ac characteristics (1) clock timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) * :the frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied pll signal is locked. parameter symbol pin name value unit unit min. typ. max. oscillation clock frequency f c x0, x1 3 16 mhz oscillation clock cycle time t c x0, x1 62.5 333 ns frequency fluctuation rate locked* d f 5 % input clock pulse width p wh p wl x0 10 ns recommended duty ratio of 40% to 60% input clock rising/falling time t cr , t cf x0 5 ns external clock operation internal operating clock frequency f cp 8.0 16 mhz pll operation 1.5 16 mhz when pll is not used internal operating clock cycle time t cp 62.5 125 ns pll operation 62.5 666 ns when pll is not used + +a fo -a - a fo d f = 100 (%) center frequency ? x0, x1 clock timing x0 t hcyl t cf p wh p wl t cr 0.8 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc
mb90550a series 34 the ac ratings are measured for the following measurement reference voltages 5.5 4.5 3.5 16 12 8 9 4 1.5 34 8 16 1.5 3 8 12 16 pll operation guarantee range internal operating clock frequency f cp (mhz) operation guarantee range mb90f553a, mb90p553a, mb90v550a relationship between oscillation clock frequency and internal operating clock frequency oscillation clock frequency f c (mhz) ? pll operation guarantee range relationship between internal operating clock frequency and power supply voltage p o w e r s u p p l y v o l t a g e v c c multiplied- by-4 multiplied- by-3 multiplied-by-2 multiplied-by-1 not multiplied internal operating clock frequency f cp (mhz) operation guarantee range mb90553a, mb90552a 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc ? input signal waveform ? output signal waveform hystheresis input pin output pin pins other than hystheresis input/md input
mb90550a series 35 (2) clock output timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) (3) reset, hardware standby input timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) parameter symbol pin name value unit remarks min. max. cycle time t cyc clk t cp ns clk - ? clk time t chcl t cp /2 - 20 t cp /2+20 ns parameter symbol pin name value unit remarks min. max. reset input time t rstl rst 16 t cp ns hardware standby input time t hstl hst 16 t cp ns clk t cyc 2.4 v 2.4 v 0.8 v t chcl rst hst 0.2 v cc t rstl , t hstl 0.2 v cc
mb90550a series 36 (4) specification for power-on reset (v cc = 5.0 v 10 %, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol pin name value unit remarks min. max. power supply rising time t r v cc 0.066 30 ms power-supply start voltage v off 0.2v power-supply end voltage v on 3.5 v power supply cut-off time t off 4 ms due to repeated operations v cc 5.0 v v cc 3.5 v 0 v v ss t r 0.2 v 0.2 v 3.5 v t off 0.2 v sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the voltage drop is 1 mv or fewer per second, however, you can use the pll clock. it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower. ram data being held
mb90550a series 37 (5) bus read timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) parameter symbol pin name value unit remarks min. max. ale pulse width t lhll ale t cp /2 - 20 ns effective address ? ale time t avll ale, a23 to a16, ad15 to ad00 t cp /2 - 20 ns ale ? address effective time t llax ale, ad15 to ad00 t cp /2 - 15 ns effective address ? rd time t avrl a23 to a16, ad15 to ad00, rd t cp - 15 ns effective address ? valid data input t avdv a23 to a16, ad15 to ad00 5 t cp /2 - 60 ns rd pulse width t rlrh rd 3 t cp /2 - 20 ns rd ? valid data input t rldv rd , ad1 to ad00 3 t cp /2 - 60 ns rd - ? data hold time t rhdx rd , ad15 to ad00 0 ns rd - ? ale - time t rhlh rd , ale t cp /2 - 15 ns rd - ? address effective time t rhax ale , a23 to a16 t cp /2 - 10 ns effective address ? clk - time t avch a23 to a16, ad15 to ad00, clk t cp /2 - 20 ns rd ? clk - time t rlch rd , clk t cp /2 - 20 ns ale ? rd time t llrl ale, rd t cp /2 - 15 ns clk ale a23 to a16 ad15 to ad00 rd t avch t lhll t avll t rlrh t rhax t rhdx t rldv t avrl t avdv t rhlh t rlch 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v t llax t llrl ?bus read timing ? multiplex mode address read data
mb90550a series 38 (6) bus write timing (v cc = 5.0 v10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) parameter symbol pin name value unit remarks min. max. effective address ? wr time t avwl a23 to a16, ad15 to ad00, wr h , wr l t cp C 15 ns wr pulse width t wlwh wrh , wr l 3 t cp /2 C 20 ns valid data output ? wr - time t dvwh ad15 to ad00, wr h , wr l 3 t cp /2 C 20 ns wr - ? data hold time t whdx ad15 to ad00, wr h , wr l 20 ns multiplex mode wr - ? address effective time t whax a23 to a16, wr h , wr l t cp /2 C 10 ns wr - ? ale - time t whlh wr h , wr l , ale t cp /2 C 15 ns wr ? clk - time t wlch wr h , wr l , clk t cp /2 C 20 ns t wlch t whlh t wlwh t avwl t dvwh t whdx t whax 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v clk ale wr a23 to a16 ad15 to ad00 (wrl, wrh) multiplex mode address write data ? bus write timing
mb90550a series 39 (7) ready input timing (v cc = 5.0 v10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) note : use the automatic ready function when the setup time for the rising edge of the rdy signal is not sufficient. parameter symbol pin name value unit remarks min. max. rdy setup time t ryhs rdy clk 45 ns rdy hold time t ryhh 0ns t ryhs t ryhh 0.8 v 2.4 v 0.8 v cc 0.2 v cc 0.8 v cc clk ale wr (wrl, wrh) rdy wait not inserted rdy wait inserted (1 cycle) ? ready input timing
mb90550a series 40 (8) hold timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) note : more than 1 machine cycle is needed before hak changes after hrq pin is fetched. (9) uart, extended i/o sirial 0, 1 timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) notes: ? these are ac ratings in the clk synchronous mode. ?c l is the load capacitance value connected to pins while testing. parameter symbol pin name value unit remarks min. max. pins in floating status ? hak time t xhal hak 30 t cp ns hak - ? pin valid time t hahv t cp 2 t cp ns parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck0 to sck2 internal shift clock mode c l = 80 pf + 1 ttl for an out- put pin 8 t cp ns sck ? sot delay time t slov sck0 to sck2, sot0 to sot2 C80 80 ns valid sin ? sck - t ivsh sck0 to sck2, sin0 to sin2 100 ns sck - ? valid sin hold time t shix sck0 to sck2, sin0 to sin2 t cp ns serial clock h pulse width t shsl sck0 to sck2 external shift clock mode c l = 80 pf + 1 ttl for an output pin 4 t cp ns serial clock l pulse width t slsh sck0 to sck2 4 t cp ns sck ? sot delay time t slov sck0 to sck2, sot0 to sot2 150 ns valid sin ? sck - t ivsh sck0 to sck2, sin0 to sin2 60 ns sck - ? valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ns hak t xhal t hahv pins high impedance ? hold timing
mb90550a series 41 (10) timer input timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) parameter symbol pin name value unit remarks min. max. input pulse width t tiwh t tiwl tin0, tin1 in0 to in3 4 t cp ns sck sot sin sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc ? internal shift clock mode ? external shift clock mode in0 to in3 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl tin0 to tin1 ? timer input timing
mb90550a series 42 (11) timer output timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) (12) trigger input timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) parameter symbol pin name value unit remarks min. max. clk - ? t out transition time t to tot0,tot1,out0, out1,ppg0 to ppg5 30 ns parameter symbol pin name value unit remarks min. max. input pulse width t trgl irq0 to irq7 5 t cp ns clk 2.4 v t to 2.4 v 0.8 v tot0,tot1 out0,out1 ppg0 to ppg5 ? timer output timing 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl irq0 to irq7 ? trigger input timing
mb90550a series 43 (13) i 2 c interface (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) notes: ? m andn in the above table represent the values of shift clock frequency setting bits (cs4 to cs0) in the clock control register iccr. for details, refer to the register description in the hardware manual. ?t dosuo represents the minimum value when the interrupt period is equal to or greater than the scl l width. ? the sda and scl output values indicate that that rise time is 0 ns. parameter symbol pin name value unit remarks min. max. internal clock cycle time t cp 62.5 666 ns all products start condition output t stao sda0 to sda2 scl0 toscl2 t cp m n/2 C 20 t cp m n/2 + 20 ns only as master stop condition output t stoo t cp (m n/2 + 4) C 20 t cp (m n/2 + 4) + 20 ns start condition detection t stai 3 t cp + 40 ns only as slave stop condition detection t stoi 3 t cp + 40 ns scl output l width t lowo scl0 to scl2 t cp m n/2 C 20 t cp m n/2 + 20 ns only as master scl output h width t higho t cp (m n/2 + 4) C 20 t cp (m n/2 + 4) + 20 ns sda output delay time t doo sda0 to sda2 scl0 to scl2 2 t cp C 20 2 t cp + 20 ns setup after sda output interrupt period t dosuo 4 t cp C 20 ns scl input l width t lowi scl0 to scl2 3 t cp + 40 ns scl input h width t highi t cp + 40 ns sda input setup time t sui sda0 to sda2 scl0 to scl2 40 ns sda input hold time t hoi 0ns
mb90550a series 44 t lowo t stao t doo t doo 189 7 689 t sui t highi t lowi t hoi t doo t doo t dosuo t stoi t sui t hoi t dosuo t higho 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc ack ack 0.8 v cc 0.8 v cc scl sda scl sda ?i 2 c interface [data transmitter (master/slave)] ?i 2 c interface [data receiver (master/slave)]
mb90550a series 45 5. a/d converter (1) electrical characteristics (4.5 v avrh - avrl, v cc = av cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to +85 c) *1: when f cp = 8 mhz, t cmp = 176 t cp . when f cp = 16 mhz, t cmp = 352 t cp . *2:equivalent to the time for conversion per channel if t smp = 64 t cp or t cmp = 352 t cp is selected when f cp = 16 mhz. *3:specifies the power-supply current (vcc = avcc = avrh = 5.0 v) when the a/d converter is inactive and the cpu has been stopped. notes: ? the error becomes larger relatively as |avrh-avrl| becomes smaller. ? use the output impedance r s of the external circuit for analog input under the following condition: external circuit output impedance r s = 10 k w max. ? if the output impedance of the external circuit is too high, the analog voltage sampling time may be insufficient. ? if you insert a dc-blocking capacitor between the external circuit and the input pin, select the capacitance about several thousands times the sampling capacitance c sh in the chip to suppress the effect of capacity potential division with c sh. parameter symbol pin name value unit remarks min. typ. max. resolution 10 bit total error 5.0 lsb non-linear error 2.5 lsb differential linearity error 1.9 lsb zero transition voltage v ot an0 to an7 avrl - 3.5lsb avrl + 0.5lsb avrl + 4.5lsb v 1lsb= (avrh - avrl) /1024 full-scale transition voltage v fst an0 to an7 avrh - 6.5lsb avrh - 1.5lsb avrh + 1.5lsb v sampling period t smp 64 4096 t cp compare time t cmp 22 m s *1 a/d conversion time t cnv 26.3 m s *2 analog port input current i ain an0 to an7 10 m a analog input voltage v ain an0 to an7 avrl avrh v reference voltage avrh avrl av cc v avrl 0 avrh v power supply current i a av cc 3.57.0 ma i ah 5 m a *3 reference voltage supply current i r avrh 300 500 m a i rh 5 m a *3 offset between channels an0 to an7 4 lsb
mb90550a series 46 r s v s r sh c sh microcontroller internal circuit input pin an0 input pin an7 external circuit analog channel selector comparator r s = 10 k w or less r sh = about 3 k w c sh = about 25 pf note: device parameter values are provided as reference values for design purposes; they are not guaranteed. s/h circuit to ? analog input circuit model
mb90550a series 47 (2) definitions of terms ? resolution: analog transition identifiable by the a/d converter. analog voltage can be divided into 1024 (2 10 ) components at 10-bit resolution. ? total error: difference between actual and logical values. this error is the sum of an offset error, gain error, non-linearity error, and an error caused by noise. ? linearity error: deviation of the straight line drawn between the zero transition point (00 0000 0000 <-> 00 0000 0001) and the full-scale transition point (11 1111 1110 <-> 11 1111 1111) of the device from actual conversion characteristics ? differential linearity error: deviation from the ideal input voltage required to shift output code by one lsb ? 10-bit a/d converter conversion characteristics 11 1111 1111 11 1111 1110 11 1111 1101 11 1111 1100 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 1lsb n + v ot v ot v nt v fst v (n + 1)t analog input 1lsb = v fst - v ot 1022 linearity error = v nt - (1lsb n + v ot ) 1lsb [ lsb ] differential linearity error = v ( n + 1 ) t - v nt 1lsb - 1 [ lsb ] linearity error digital output
mb90550a series 48 n example characteristics 1. l level output voltage 700 600 500 400 300 200 100 0 0246810 i ol (ma) v ol (mv) v cc = 3.5 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v t a = 25 c 700 600 500 400 300 200 100 0 0 5 10 15 i ol (ma) v ol (mv) 20 25 30 v ol - i ol other than p20 to p27 v ol - i ol p20 to p27
mb90550a series 49 2. h level output voltage 3. h level input voltage / l level input voltage (cmos input) v cc = 3.5 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v t a = 25 c 700 600 500 400 300 200 100 0 0 - 2 - 4 - 6 - 8 - 10 i oh (ma) v cc - v oh (mv) (v cc - v oh ) - i oh other than p50 to p55 5 4.5 4 3.5 3 2.5 2 1.5 1 1.5 0 3.5 4 4.5 5 5.5 v cc (v) v ih /v il (v) t a = 25 c v ih / v il - v cc
mb90550a series 50 4. h level input voltage / l level input voltage (cmos hysteresis input ) 5 4.5 4 3.5 3 2.5 2 1.5 1 1.5 0 3.5 4 4.5 5 5.5 v ihl v ihs v cc (v) v ihs /v ils (v) t a = 25 c v ihs / v ils - v cc
mb90550a series 51 5. power supply current (f cp = internal operating clock frequency) 30 25 20 15 10 5 0 3.5 4 4.5 5 5.5 f cp = 8 mhz v cc (v) i cc (ma) f cp = 10.6 mhz f cp = 16 mhz t a = 25 c f cp = 4 mhz 10 9 8 7 5 6 4 3 2 1 0 3.5 4 4.5 5 5.5 f cp = 8 mhz v cc (v) i ccs (ma) f cp = 10.6 mhz f cp = 16 mhz t a = 25 c f cp = 4 mhz i cc - v cc i ccs - v cc ? mb90552a ? measurement conditions : external clock mode, rom read loop operation, without resource operation, typ. sample, internal operating frequency = 4mhz (external rectangular wave clock at 8mhz), t a = 25 c
mb90550a series 52 70 60 50 40 30 20 10 4.5 5 5.5 f cp = 4 mhz f cp = 10 mhz v cc (v) i cc (ma) f cp = 16 mhz t a = 25 c 12 10 8 6 4 2 0 4.5 5 5.5 t a = 25 c f cp = 16 mhz f cp = 4mhz f cp = 10 mhz v cc (v) i ccs (ma) i cc - v cc i ccs - v cc ? mb90f553a ? measurement conditions : external clock mode, rom read loop operation, without resource operation, typ. sample, internal operating frequency = 4mhz (external rectangular wave clock at 8mhz), t a = 25 c
mb90550a series 53 6. pull-up resistance t a = 85 c t a = 25 c t a = - 40 c 90 80 70 60 50 40 30 20 10 4 4.5 5 5.5 v cc (v) pull-up resistance - v cc pull-up resistance (k w )
mb90550a series 54 n instructions (340 instructions) table 1 explanation of items in tables of instructions ? number of execution cycles the number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal rom connected to a 16-bit bus is fetched. if data access is interfered with, therefore, the number of execution cycles is increased. for each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. if data access in interfered with, therefore, the number of execution cycles is increased. when a general-purpose register, an internal rom, an internal ram, an internal i/o device, or an external bus is accessed during intermittent cpu operation, the cpu clock is suspended by the number of cycles specified by the cg1/0 bit of the low-power consumption mode control register. when determining the number of cycles required for instruction execution during intermittent cpu operation, therefore, add the value of the number of times access is done the number of cycles suspended as the corrective value to the number of ordinary execution cycles. item meaning mnemonic upper-case letters and symbols: represented as they appear in assembler. lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction code. # indicates the number of bytes. ~ indicates the number of cycles. m : when branching n : when not branching see table 4 for details about meanings of other letters in items. rg indicates the number of accesses to the register during execution of the instruction. it is used calculate a correction value for intermittent operation of cpu. b indicates the correction value for calculating the number of actual cycles during execution of the instruction. (table 5) the number of actual cycles during execution of the instruction is the correction value summed with the value in the ~ column. operation indicates the operation of instruction. lh indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. z : transfers 0. x : extends with a sign before transferring. C : transfers nothing. ah indicates special operations involving the upper 16 bits in the accumulator. * : transfers from al to ah. C : no transfer. z : transfers 00 h to ah. x : transfers 00 h or ff h to ah by signing and extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). * : changes due to execution of instruction. C : no change. s : set by execution of instruction. r : reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : instruction is a read-modify-write instruction. C : instruction is not a read-modify-write instruction. note: a read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
mb90550a series 55 table 2 explanation of symbols in tables of instructions symbol meaning a 32-bit accumulator the bit length varies according to the instruction. byte : lower 8 bits of al word : 16 bits of al long : 32 bits of al and ah ah al upper 16 bits of a lower 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 direct addressing physical direct addressing bit 0 to bit 15 of addr24 bit 16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) imm4 imm8 imm16 imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address rel pc relative addressing ear eam effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list
mb90550a series 56 table 3 effective address fields note : the number of bytes in the address extension is indicated by the + symbol in the # (number of bytes) column in the tables of instructions. code notation address format number of bytes in address extension * 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
mb90550a series 57 table 4 number of execution cycles for each type of addressing note : (a) is used in the ~ (number of states) column and column b (correction value) in the tables of instructions. table 5 compensation values for number of cycles used to calculate number of actual cycles notes: (b), (c), and (d) are used in the ~ (number of states) column and column b (correction value) in the tables of instructions. when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. table 6 correction values for number of cycles used to calculate number of program fetch cycles notes: when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for worst case calculations. code operand (a) number of register accesses for each type of addressing number of execution cycles for each type of addressing 00 to 07 ri rwi rli listed in tables of instructions listed in tables of instructions 08 to 0b @rwj 2 1 0c to 0f @rwj + 4 2 10 to 17 @rwi + disp8 2 1 18 to 1b @rwj + disp16 2 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (c) word (d) long cycles access cycles access cycles access internal register +0 1 +0 1 +0 2 internal memory even address internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 even address on external data bus (16 bits) odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 external data bus (8 bits) +1 1 +4 2 +8 4 instruction byte boundary word boundary internal memory +2 external data bus (16 bits) +3 external data bus (8 bits) +3
mb90550a series 58 table 7 transfer instructions (byte) [41 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov ri, ear mov ri, eam mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah /mov @a, t xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) +disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z x x x x x x x x x x C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * * * * * * * C * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90550a series 59 table 8 transfer instructions (word/long word) [38 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw dir, a movw addr16, a movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw @al, ah /movw@a, t xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C movl a, ear movl a, eam movl a, #imm32 movl ear, a movl eam, a 2 2+ 5 2 2+ 4 5+ (a) 3 4 5+ (a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C C C C C C C C C C C
mb90550a series 60 table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) Cimm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C C C * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) +(ear) word (a) ? (a) +(eam) word (a) ? (a) +imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) Cimm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 6 7+ (a) 4 6 7+ (a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) +imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) Cimm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
mb90550a series 61 table 10 increment and decrement instructions (byte/word/long word) [12 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+ (a) 7 9+ (a) 4 0 4 0 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * mnemonic # ~ rg b operation lh ah i s t n z v c rmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (ah) C (al) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (ah) C (al) word (a) ? (ear) word (a) ? (eam) word (a) ? imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (a) ? (ear) word (a) ? (eam) word (a) ? imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
mb90550a series 62 table 12 multiplication and division instructions (byte/word/long word) [11 instructions] *1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. *2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when the result is zero or when an overflow occurs, and 2 (b) normally. *7: (c) when the result is zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not zero. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not zero. *12: 4 when word (ear) is zero, and 12 when word (ear) is not zero. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 1 0 1 0 0 1 0 0 1 0 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (ear) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
mb90550a series 63 table 13 signed multiplication and division instructions (byte/word/long word) [11 instructions] *1: set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. *2: set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. *3: set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. *4: positive dividend: set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. negative dividend: set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: positive dividend: set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. negative dividend: set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: when the division-by-0, (b) for an overflow, and 2 (b) for normal operation. *7: when the division-by-0, (c) for an overflow, and 2 (c) for normal operation. *8: set to 3 when byte (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *9: set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: set to 3 when word (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *12: set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. notes: ? when overflow occurs during div or divw instruction execution, the number of execution cycles takes two values because of detection before and after an operation. ? when overflow occurs during div or divw instruction execution, the contents of al are destroyed. ? for (a) to (d), refer to table 4 number of execution cycles for effective address in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw div a div a, ear div a, eam divw a, ear divw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 2 2 2 + 2 2+ 2 2 2 + 2 2 2 + *1 *2 *3 *4 *5 *8 *9 *10 *11 *12 *13 0 1 0 1 0 0 1 0 0 1 0 0 0 *6 0 *7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
mb90550a series 64 table 14 logical 1 instructions (byte/word) [39 instructions ] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C * C C C C * C C C C * C C * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C C * C C C C C * C C C C C * C C *
mb90550a series 65 table 15 logical 2 instructions (long word) [6 instructions] table 16 sign inversion instructions (byte/word) [6 instructions] table 17 normalize instruction (long word) [1 instruction] *1: 4 when the contents of the accumulator are all zeroes, 6 + (r0) in all other cases (shift count). note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ea xorl a, eam 2 2+ 2 2+ 2 2+ 6 7+ (a) 6 7+ (a) 6 7+ (a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah i s t n z v c rmw neg a neg ear neg eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ rg b operation lh ah i s t n z v c rmw nrml a, r0 2 * 1 1 0 long (a) ? shift until first digit is 1 byte (r0) ? current shift count CCCCCC*CC C
mb90550a series 66 table 18 shift instructions (byte/word/long word) [18 instructions] *1: 6 when r0 is 0, 5 + (r0) in all other cases. *2: 6 when r0 is 0, 6 + (r0) in all other cases. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+ (a) 3 5+ (a) * 1 * 1 * 1 0 0 2 0 2 0 1 1 1 0 0 0 2 (b) 0 2 (b) 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C * C * C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 1 1 1 2 2 2 2 2 2 * 1 * 1 * 1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * r * * * * * * * * * * C C C C C C * * * * * * C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 2 2 2 * 2 * 2 * 2 1 1 1 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C * * C * * * * * * C C C * * * C C C
mb90550a series 67 table 19 branch 1 instructions [31 instructions] *1: 4 when branching, 3 when not branching. *2: (b) + 3 (c) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) r branch address. *7: save (long word) to stack. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 11+ (a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15, (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 to 15, (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15, (pcb) ? (eam) 16 to 23 word (pc) ? addr0 to 15, (pcb) ? addr16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90550a series 68 table 20 branch 2 instructions [19 instructions] *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: set to 3 (b) + 2 (c) when an interrupt request occurs, and 6 (c) for return. *8: retrieve (word) from stack *9: retrieve (long word) from stack *10: in the cbne/cwbne instruction, do not use the rwj+ addressing mode. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel* 10 cwbne ear, #imm16, rel cwbne eam, #imm16, rel* 10 dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti link #local8 unlink ret * 8 retp * 9 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 * 1 * 1 * 2 * 3 * 4 * 3 * 5 * 6 * 5 * 6 20 16 17 20 15 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) * 7 (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (eam) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * C C C C C C C C C C C C C C s s s s * C C C C C C C C C C C C C C C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * C C C C C C C C * C C C C C C C C C C C * C * C C C C C C C C C
mb90550a series 69 table 21 other control instructions (byte/word/long word) [36 instructions] *1: pcb, adb, ssb, usb, and spb : 1 state dtb, dpr : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) C 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: pop count (c), or push count (c) *5: pop count or push count. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 * 3 3 3 4 * 2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 * 1 1 1 1 1 1 1 1 1 0 0 0 * 5 0 0 0 * 5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) +2 word (ah) ? ((sp)), (sp) ? ( sp) +2 word (ps) ? ((sp)), (sp) ? ( sp) +2 (rlst) ? ((sp)), (sp) ? (sp) +2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? (sp) +ext (imm8) word (sp) ? (sp) +imm16 byte (a) ? (brgl) byte (brg2) ? (a) no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no flag change prefix code for common register bank C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90550a series 70 table 22 bit manipulation instructions [21 instructions] *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: undefined count *5: until condition is satisfied note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 23 accumulator manipulation instructions (byte/word) [6 instructions] mnemonic # ~ rg b operation lh ah i s t n z v c rmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 * 1 * 1 * 2 * 1 * 1 * 2 * 3 * 4 * 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 5 * 5 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C mnemonic # ~ rg boperation lh ah i s t n z v c rmw swap swapw ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a) 0 to 7 ? (a) 8 to 15 word (ah) ? (al) byte sign extension word sign extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C
mb90550a series 71 table 24 string instructions [10 instructions] m: rw0 value (counter value) n: loop count *1: 5 when rw0 is 0, 4 + 7 (rw0) for count out, and 7 n + 5 when match occurs *2: 5 when rw0 is 0, 4 + 8 (rw0) in any other case *3: (b) (rw0) + (b) (rw0) when accessing different areas for the source and destination, calculate (b) sepa- rately for each. *4: (b) n *5: 2 (rw0) *6: (c) (rw0) + (c) (rw0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) n *8: 2 (rw0) note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 5 * 5 * 5 * 5 * 5 * 3 * 3 * 4 * 4 * 3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval (@ah+) C al, counter = rw0 byte retrieval (@ahC) C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 8 * 8 * 8 * 8 * 8 * 6 * 6 * 7 * 7 * 6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval (@ah+) C al, counter = rw0 word retrieval (@ahC) C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
mb90550a series 72 n ordering information part number package remarks mb90552apf mb90553apf mb90t552apf mb90t553apf mb90f553apf MB90P553APF 100-pin plastic qfp (fpt-100p-m06) mb90552apf mb90553apf mb90t552apf mb90t553apf mb90f553apf MB90P553APF 100-pin plastic lqfp (fpt-100p-m05)
mb90550a series 73 n package dimensions 100-pin plastic qfp (fpt-100p-m06) dimensions in mm (inches) 100-pin plastic lqfp (fpt-100p-m05) dimensions in mm (inches) c 1994 fujitsu limited f100008-3c-2 "a" "b" 0.10(.004) 0.53(.021)max 0.18(.007)max details of "a" part 0 10 details of "b" part 12.35(.486) ref 16.30?.40 (.642?016) 0.05(.002)min (stand off) 0.15?.05(.006?002) index 23.90?.40(.941?016) 20.00?.20(.787?008) 17.90?.40 14.00?.20 (.551?008) (.705?016) 0.13(.005) m 18.85(.742)ref 22.30?.40(.878?016) 1 30 31 50 51 80 81 100 0.25(.010) 0.30(.012) 0.65(.0256)typ 0.30?.10 (.012?004) lead no. 0.80?.20 (.031?008) 3.35(.132)max (mounting height) c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.00?.20(.630?008)sq 14.00?.10(.551?004)sq 0.50(.0197)typ .007 ?001 +.003 ?.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?004 +.008 ?.10 +0.20 1.50 .005 ?001 +.002 ?.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.50?.20(.020?008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.10?.10 (.004?004) (stand off) 0~10 lead no. (mouting height)
mb90550a series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9910 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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